[Libre-soc-bugs] [Bug 755] add grev

[bugzilla-daemon at libre-soc.org]

https://bugs.libre-soc.org/show_bug.cgi?id=755

--- Comment #1 from Luke Kenneth Casson Leighton <lkcl at lkcl.net> ---
commit 7aed55e3538fb39327bf4946843292d128d29abc (HEAD -> master, origin/master,
origin/HEAD)
Author: Luke Kenneth Casson Leighton <lkcl at lkcl.net>
Date:   Sat Dec 11 15:29:09 2021 +0000

    add some comments (locations for comments to be added)

i took a quick look, one thing: i think you'll probably find this works:


        # start with input as first layer
        step_i = self.input

        for i in range(self.log2_width):
            step_o = Signal(self.width, name=f"step{i}")
            chunk_size = 1 << i
            # TODO comment that this is creating the mux-swapper
            with m.If(self.chunk_sizes[i]):
                # swap path
                for j in range(self.width):
                    # TODO explain what this XOR does
                    m.d.comb += step_o[j].eq(step_i[j ^ chunk_size])
            with m.Else():
                # straight path
                m.d.comb += step_o.eq(step_i)
            # output becomes input for next phase
            step_i = step_o
        # TODO comment that the last "step" is the output
        m.d.comb += self.output.eq(step_o)

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