[Libre-soc-bugs] [Bug 651] Convert bitmap images to vector svg - multi i/o dep cell and multi func unit

bugzilla-daemon at libre-soc.org bugzilla-daemon at libre-soc.org
Fri Aug 20 12:51:50 BST 2021


Luke Kenneth Casson Leighton <lkcl at lkcl.net> changed:

           What    |Removed                     |Added
 total budget (EUR)|250                         |300
  for completion of|                            |
       task and all|                            |
           subtasks|                            |
   budget (EUR) for|250                         |300
         this task,|                            |
          excluding|                            |
   subtasks' budget|                            |

--- Comment #11 from Luke Kenneth Casson Leighton <lkcl at lkcl.net> ---
(In reply to vklr at vkten.in from comment #10)
> Created attachment 139 [details]
> svg image of dependence_cell_multi_pending.jpg
> SVG image of dependence_cell_multi_pending.jpg
> Please review.

love the layout, it's very clear.  two things which will significantly
improve it (see these):


(1) there are places where the wires cross.  because there are no
    colours, you can't work out which wires "join" and which "cross".

    could you put "dots" at the crossing points, like in the JPG?

(2) once all the dots are there, could you colourise the wires
    that are all the same signal?

    (no need to do everything)

i made a start on the colours but i messed some of them up, i don't
know how.

mainly the named inputs, and the named outputs, try to make them
REALLY bright primary colours, lots of contrast.

i leave it to you to decide the best ones?

again, you don't need to do *everything* in colour, but at least
everything that has an input name and an output name.

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