[Libre-soc-bugs] [Bug 657] unit tests needed for BCD instructions

bugzilla-daemon at libre-soc.org bugzilla-daemon at libre-soc.org
Thu Aug 19 18:02:13 BST 2021


--- Comment #14 from Luke Kenneth Casson Leighton <lkcl at lkcl.net> ---
(In reply to dmitry.selyutin from comment #13)
> Hi Luke, I think I finally got it. Since the recent commits, we do the
> following:
> 1. Use VHDL algorithm as a reference implementation.

yes. full_adder64 (much as i like it) can be replaced with just
(in python) "return a + b", and everywhere x[N] replaced with
"(x>>N) & 0b1" or if in a test: "if x&(1<<N)"

the idea is that the code should be simple and obviously readable

> 2. Instead of this fun with adders, we rely on big ints.

yes.  but try to make it "obvious" and/or add comments.  instead of:

     addg6s[lo + 3] = 0
     addg6s[lo + 2] = 1
     addg6s[lo + 1] = 1
     addg6s[lo + 0] = 0


     addg6s |= 0b0110 << lo

> 3. Instead of generating the product, we generate random BCDs.

yyyeah, lots of them.  _hopefully_ that will spam enough numbers
at the pseudocode to give enough coverage, i.e. for the carry
bit to be triggered with both 0 and 1 with an equal distribution.

carry on two random numbers is a 50-50 probability, right? because
it uses (ultimately) XOR?

> 4. And yes, we can batch it!


btw do keep to under an 80 char limit.  two reasons: we cannot assume
that all developers have massive hi-res screens (the recent new
developers from India will not), and second, i use hi-res screens to
get *more terminals* on-screen ==>  more information, more depth of
investigation, less work, less effort.

You are receiving this mail because:
You are on the CC list for the bug.

More information about the libre-soc-bugs mailing list