[Libre-soc-bugs] [Bug 657] unit tests needed for BCD instructions

[bugzilla-daemon at libre-soc.org]

https://bugs.libre-soc.org/show_bug.cgi?id=657

--- Comment #12 from Luke Kenneth Casson Leighton <lkcl at lkcl.net> ---
i tracked this down:

https://github.com/antonblanchard/microwatt/blob/master/execute1.vhdl#L528

it's an implementation of addg6s in VHDL.  the sum_with_carry variable
is adding its two inputs, a and b, with an extra (65th) bit, just like
we did in the pseudocode.

what i would suggest is, simply creating a python function which does
the equivalent of the pseudocode (and check it's the same as the microwatt
version), and just make up some values to test.

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