[Libre-soc-bugs] [Bug 469] Create D-cache from microwatt dcache.vhdl

[bugzilla-daemon at libre-soc.org]

https://bugs.libre-soc.org/show_bug.cgi?id=469

Luke Kenneth Casson Leighton <lkcl at lkcl.net> changed:

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                 CC|                            |cestrauss at gmail.com

--- Comment #37 from Luke Kenneth Casson Leighton <lkcl at lkcl.net> ---
http://lists.libre-soc.org/pipermail/libre-soc-dev/2021-April/002444.html

i have a suspicion as to what is going on.  that there is not a problem
with dcache.py: instead it is part of Wishbone WB3 (simple) WB4 (pipeline)
interaction.

WB4 spec, section 5.3

5.3     Simple slaves directly supporting pipelined mode

Even though not initially designed for pipelined mode many simple wishbone
slaves
directly support this mode. For this to be true the following characteristics
must be true

   1. [ACK_O] should be registered
   2. a read or write classic bus cycle should always occupy two clock cycles
   3. actual write to internal register must be done on rising clock edge 1.
       See figure 5-3 below

Master input signal [STALL_I] should be tied low, inactive, statically.

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