[Libre-soc-dev] dcache investigation

[Luke Kenneth Casson Leighton]

am currently looking at the microwatt dcache port.  it is strange in that
it is both complex and yet straightforward, combined.

there is a wishbone interaction issue when stall is enabled, which is
giving grief.  all our wishbone devices and buses are "simple" ones, where
microwatt assumes "pipeline" mode (an extra signal, called "stall")

it turns out to be possible to connect simple slaves to pipelined masters
according to section 5.2.1 of the WB4 spec by setting stall = cyc & ~ack.

unfortunately this simply delays the acceptance of the data within dcache
by one cycle, whilst the address remains the same, and the cache rams end
up with out of sync data.

if the WB stall signal is not set, no problem occcurs.

i have no idea what to do.

l.



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