[Libre-soc-bugs] [Bug 620] post-layout simulation needed using cocotb

[bugzilla-daemon at libre-soc.org]

https://bugs.libre-soc.org/show_bug.cgi?id=620

--- Comment #16 from Luke Kenneth Casson Leighton <lkcl at lkcl.net> ---
currently doing ghdl cocotb post layout P&R using the cts.vst files.

both chip.vst / chip_r.vst and corona are a bit of a mess:

* to/from pad signals exist which have the same name as the chip in/out ports
* the names iovdd gpio iovss vdd and vss are used for both components and
signals (niolib)
* gpio in niolib uses std_ulogic for the pad port but in chip/chip_r it is
declared as a bit.

some of these can be corrected with post-processing, others involve renaming
niolib cell components, others need the corona/chip generation to be updated.

quite a lot to do

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