[Libre-soc-bugs] [Bug 620] post-layout simulation needed using cocotb

[bugzilla-daemon at libre-soc.org]

https://bugs.libre-soc.org/show_bug.cgi?id=620

--- Comment #15 from Staf Verhaegen <staf at fibraservi.eu> ---
Out of discussion on IRC here minimal clock generation block in VHDL:

    entity clkgen is port(clk: out bit);
    end entity clkgen;

    architecture sim of clkgen is
    signal intclk: bit := '0';
    begin
        intclk <= not intclk after 10 ns;
        clk <= intclk;
    end architecture sim;

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