[Libre-soc-bugs] [Bug 517] Define JTAG pins and set up with litex for ulx3s85f

bugzilla-daemon at libre-soc.org bugzilla-daemon at libre-soc.org
Sun Apr 11 03:39:37 BST 2021


--- Comment #120 from Luke Kenneth Casson Leighton <lkcl at lkcl.net> ---
(In reply to Cole Poirier from comment #119)

> Because you said to remove the VREF jumper cable

no, i did not. read comment #102 agsin.

jumper != the wire.  jumper == a 5 x 8mm black connector between two pins.

read comment #102 again.  look at the photo.  where does it say the word CABLE?

you are not paying attention and are adding random words.

this is the source of the confusion.

> because VREF is supplied
> by the FPGA, therefore there is not a pin connected for VREF, because it is
> supplied by the FPGA?

if the cable is removed there is not a way for the power from the FPGA to get
to VREF on the FT232, is there?

power cannot magically travel through the air, can it?

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