[Libre-soc-bugs] [Bug 517] Define JTAG pins and set up with litex for ulx3s85f

bugzilla-daemon at libre-soc.org bugzilla-daemon at libre-soc.org
Fri Apr 9 22:13:08 BST 2021


Luke Kenneth Casson Leighton <lkcl at lkcl.net> changed:

           What    |Removed                     |Added
                URL|                            |https://libre-soc.org/HDL_w
                   |                            |orkflow/ECP5_FPGA/

--- Comment #100 from Luke Kenneth Casson Leighton <lkcl at lkcl.net> ---
(In reply to Cole Poirier from comment #98)

> Should I leave the voltage and ground pins of the ft232r interface
> unconnected to prevent voltage fighting with the fpga power connector?

hmmmm.... on the FT232 that i have here, there is a voltage selector
jumper (5.5v -> VREF <- 3.3v).

strictly speaking the FPGA VREF should be connected to that middle pin
in order to provide VREF.

You are receiving this mail because:
You are on the CC list for the bug.

More information about the libre-soc-bugs mailing list