[Libre-soc-bugs] [Bug 620] post-layout simulation needed using cocotb

[bugzilla-daemon at libre-soc.org]

https://bugs.libre-soc.org/show_bug.cgi?id=620

--- Comment #9 from Luke Kenneth Casson Leighton <lkcl at lkcl.net> ---
ok the cxxrtl compilation of ls180, including the litex peripheral set, was
successful.  took several minutes to compile.

results of running an openocd jtagremote "upload" are that the wishbone
interface is not entirely functional yet.

however the DMI interface, which allows the core to be stopped, reset, and
restarted, was successful.

because cxxsim can output gtkwave VCD i was able to ascertain that the core is
executing at address 0x700 in a loop, which is a good sign.

investigating wishbone over jtag is the next priority.

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