[Libre-soc-bugs] [Bug 517] Define JTAG pins and set up with litex for ulx3s85f

bugzilla-daemon at libre-soc.org bugzilla-daemon at libre-soc.org
Mon Apr 5 18:06:19 BST 2021


--- Comment #87 from Cole Poirier <colepoirier at gmail.com> ---
(In reply to Luke Kenneth Casson Leighton from comment #86)
> (In reply to Cole Poirier from comment #78)
> > > > Do you know of a jtag usb adapter that supports softcore targets?
> > > 
> > > i don't
> > 
> > Isn't that a problem as we are using a softcore and using gpio pins to do
> > jtag instead of the stm module on the fpga?
> you have confused multiple things.
> * openocd talks to stlinkv2.
> * stlinkv2 is instructed to enter JTAG MODE
> at that point it doesn't matter what the hell gets connected, it's just JTAG.
> * four wires speaking JTAG connect to FPGA
> * those pins are connected to HDL
> * that HDL understands JTAG
> the "softcore" isn't even directly associated with JTAG, they are completely
> separate subsystems.  the "softcore" does not know anything at all about
> the JTAG *protocol* is implemented in HDL by Staf's C4M-JTAG nmigen module.
> that is its job.
> what you are referring to, "is there a jtag usb that supports softcore
> targets" completely confuses about four unrelated things, including assuming
> that the HIGH LEVEL scripts in openocd are relevant and mandatory.
> we are doing LOW LEVEL and the rest of openocd is completely and utterly
> irrelevant at this early phase.
> the only reason we are using openocd is because it contains a tiny relevant
> fraction of code necessary to recognise the stlinkv2 and get it into JTAG
> mode.

Ok, understood. Thanks for your help with openocd and in clearing up my
confusion. How do I go about defining a target now that the stlink<->openocd
communication is properly set up.

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