[Libre-soc-bugs] [Bug 199] Layout using coriolis2 main core, 180nm

[bugzilla-daemon at libre-soc.org]

https://bugs.libre-soc.org/show_bug.cgi?id=199

--- Comment #91 from Luke Kenneth Casson Leighton <lkcl at lkcl.net> ---
the P&R completed for the whole chip, including the PowerISA core this time.
it is 4x bigger @ 26,000 x 26,000 lambda

nohup.out is here: https://ftp.libre-soc.org/nohup.out.bz2

3 horiz not routed, 2 vertical, but 7,000 unrouted segments.

could the introduction of a clock tree (USE_CLOCKTREE=yes in Makefile)
have an effect?

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