[Libre-soc-bugs] [Bug 199] Layout using coriolis2 main core, 180nm

[bugzilla-daemon at libre-soc.org]

https://bugs.libre-soc.org/show_bug.cgi?id=199

--- Comment #88 from Staf Verhaegen <staf at fibraservi.eu> ---

> * Litex provides peripherals however the IO for UART and GPIO need to
>   be routed *through JTAG*

Actually all IO should be routed through JTAG, thus also SDRAM, PWM, SPI, ...
This allows standardized PCB testing without tester need to write power
programs etc.

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