[Libre-soc-bugs] [Bug 508] decide package size and pin allocation for 180nm ASIC

[bugzilla-daemon at libre-soc.org]

https://bugs.libre-soc.org/show_bug.cgi?id=508

--- Comment #8 from Luke Kenneth Casson Leighton <lkcl at lkcl.net> ---
(In reply to Jacob Lifshay from comment #6)
> I didn't check which packages have what, but I think we should get a package
> with a metal bottom

Exposed Pad.

> since our test chip could use a few watts at 300MHz and
> be harder to cool in just a plastic package. I'm assuming the cost of the
> packages is small enough to be negligible.

mmm except it is "pin 129" (usually connected to GND) and we'd have to find out
how that's wired up.  or if it's safe to ignore.  or if it affects how the
ioring must be organised (33-32-32-32)?

then communicate that to jean-paul, who would need to tell us if it can
be supported in coriolis2, and how, and how much time it would take.

something as simple as "which package" has so many implications!

bottom line, if we have to run at a lower speed then this is less risk
than trying to add extra time which we may not have.  the heat can be
"solved" with the application of some coolant spray... :)

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