[Libre-soc-bugs] [Bug 485] Create I-Cache from microwatt icache.vhdl

[bugzilla-daemon at libre-soc.org]

https://bugs.libre-soc.org/show_bug.cgi?id=485

--- Comment #12 from Cole Poirier <colepoirier at gmail.com> ---
(In reply to Luke Kenneth Casson Leighton from comment #9)
> 1243 #               -- Requests are all sent if stb is 0
> 1244 #               stbs_done := r.wb.stb = '0';
> 1245                 # Requests are all sent if stb is 0
> 1246                 sync += stbs_done.eq(r.wb.stb == 0)
> 
> likewise stbs_done will here be set ONLY ON THE NEXT CYCLE yet the
> expectation is clearly for use in this FSM state.
> 
> you want comb += just like i did in dcache.

Done. This reqires making the following change as well:
```
1264    # That was the last word ?
1265    # We are done sending.
1266    # Clear stb and set stbs_done
1267    # so we can handle
1268    # an eventual last ack on
1269    # the same cycle.
1270    with m.If(is_last_row_addr(r.wb.adr, r.end_row_ix)):
1271        sync += r.wb.stb.eq(0)
1272        comb += stbs_done.eq(1)
```

r is driven by sync domain in the rest of the function/process, is the above
correct?

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