[Libre-soc-bugs] [Bug 490] Complete peripheral set including litex for first functional POWER9 Core

[bugzilla-daemon at libre-soc.org]

https://bugs.libre-soc.org/show_bug.cgi?id=490

--- Comment #26 from Luke Kenneth Casson Leighton <lkcl at lkcl.net> ---
(In reply to Luke Kenneth Casson Leighton from comment #25)

> > For
> > higher level implementation is to integrate JTAG interface inside the nmigen
> > platform.
> 
> yes, that's 

an unfinished sentence :)

that's what i've done.  everything is declared back in nmigen:

* TAP.add_ios
* TAP.add_wishbone
* TAP.add_dmi

otherwise we cannot run nmigen simulation unit tests of the IOConns.

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