[Libre-soc-bugs] [Bug 499] Create experimental gdb protocol implementation in nmigen for debugging

[bugzilla-daemon at libre-soc.org]

https://bugs.libre-soc.org/show_bug.cgi?id=499

--- Comment #11 from Luke Kenneth Casson Leighton <lkcl at lkcl.net> ---
(In reply to Staf Verhaegen from comment #7)
> I think you guys are mixing up layers. JTAG is a communication interface not
> a protocol. A debugging protocol is something you can add on top. 

in terms of those defined keywords: jacob is talking about implementing the
actual gdb serial debugging protocol in nmigen RTL.

given that the JTAG RTL works and has openocd to act as a gateway between
gdb and JTAG, which does exactly the same job, i am not sure why this is
continuing to be discussed, given that it is taking up precious time.

> AFAIK ARM defines a standard set of JTAG instructions and if a CPU
> implements these one can use OpenOCD to setup a debug server for debugging
> the ARM CPU remotely using gdb.

yes.  and the RISC-V Debug Working Group defined something similar (they
used DMI addresses then proxied DMI over JTAG), then made a patch to openocd
to support those.

> So to me the question is if a similar set of debugging JTAG instructions
> exists for Power and if OpenOCD or another program has support for this.

i checked: there was a very old reverse-engineered 32-bit powerpc processor
effort (Power 2.07?) that did not make it into upstream openocd.  of course
that is *their* defined JTAG registers / formats.

i found a really old patch for or1k on the openocd mailing list which looked
pretty straightforward.

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