[Libre-soc-bugs] [Bug 490] Complete peripheral set including litex for first functional POWER9 Core

[bugzilla-daemon at libre-soc.org]

https://bugs.libre-soc.org/show_bug.cgi?id=490

--- Comment #23 from Luke Kenneth Casson Leighton <lkcl at lkcl.net> ---
sfaf should i be calling c4m_jtag TAP.add_io for *all* pins?  that
seems somewhat excessive, and now that i think about it it's a *lot* of
work:

* call add_ios in nmigen
* expose both the pad wires *and* the the jtag-io wires (IOConn Record)
* add all IOConn records to the litex libresoc core.py code
* get litex to generate the ls180.v
* join up the libresoc core (in verilog) to ls180.v
* re-import ls180.v into nmigen
* *finally* wire up the connections between jtag-io and pads

i might actually do that last step in litex (ls180soc.py) to save some
messing about, and reduce the number of wires routed between different
compilers.

so if it's ok with you i'm going to do the 16 GPIO, and the 2nd UART.
this will cover:

* IOType.In (uart1 rx)
* IOType.Out (uart1 rx)
* IOType.InTriOut (gpios 0-15 yes i worked out how to do o/i/oe)

also: do you have a template for re-building the actual SoC with the
c4m IO cells?  i can throw something together if not but i will need
some guidance / pointer-to-some-code.

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