[Libre-soc-bugs] [Bug 499] Create experimental gdb protocol implementation in nmigen for debugging

[bugzilla-daemon at libre-soc.org]

https://bugs.libre-soc.org/show_bug.cgi?id=499

--- Comment #1 from Luke Kenneth Casson Leighton <lkcl at lkcl.net> ---
see what you can do, jacob, you will find a serial tx rx implementation in
nmigen-soc i believe, which will save some time.

the tricky bit is that it will need to connect to DMI (with suitable converter)
and there is already one "thing" connecting to that (DMI2JTAG).  switching
between the two could be muxed with an external pin.

also a memory (wishbone master) interface is needed, which Staf's code already
provides, and it took me about 2-3 hours to work that out and hook it up with a
unit test first.

normally i'd estimate overall it would be about... 3 to 5 days total here which
starts to put it outside of the "code freeze" zone.

examine the git commits from the past 3 days. you will find i created a dummy
(fake) DMI server nmigen test process which pretends to support DMI address 0
(read and write) and DMI.MSR (read only)

if you can implement it REAL fast and get a wishbone master and DMI gateway
done in under 2 days then we can put it in.

one extra wishbone master is not a problem, no MUXing needed, litex just adds
it to the list of things to hook up.

basically, go for it but be QUICK ok?

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