[Libre-soc-bugs] [Bug 490] Complete peripheral set including litex for first functional POWER9 Core

[bugzilla-daemon at libre-soc.org]

https://bugs.libre-soc.org/show_bug.cgi?id=490

--- Comment #18 from Luke Kenneth Casson Leighton <lkcl at lkcl.net> ---
(In reply to Staf Verhaegen from comment #17)
> Would be strange if such a bug would be there as I successfully tested JTAG
> interface with openocd on FPGA.
> See for example this video:
> https://chips4makers.io/blog/blink-demo.html#blink-demo
> I don't know though if this was still using the VHDL version of the JTAG
> interface or the nmigen one.

this is pure nmigen (c4m).

i got it to "work" with this in openocd:

jtag newtap libresoc tap -irlen 4 -irmask 0xf -ircapture 0xf -expected-id
0x000018ff

> Anyway won't have time in near future to look deeper into this.

ok.  i will investigate more in-depth tomorrow after sorting out some
alternative to openocd.

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