[Libre-soc-bugs] [Bug 493] DMI JTAG SERDES needed, to be translated from microwatt/dmi_dtm_xilinx.vhdl

[bugzilla-daemon at libre-soc.org]

https://bugs.libre-soc.org/show_bug.cgi?id=493

--- Comment #3 from Luke Kenneth Casson Leighton <lkcl at lkcl.net> ---
https://www2.lauterbach.com/pdf/training_jtag.pdf

this says, "Reading or writing the IR or DR is performed bitwise from LSB to
MSB. With every bit shifted into the TAP controller via TDI, the contents of DR
is rightshifted one bit, providing the LSB on TDO."

this seems to be ok:

            # tdo = reg[0], tdo_en = shift
            tdos.append((reg[0], sr_shift))

and yes, this seems to be ok:

                m.d.posjtag += reg.eq(Cat(reg[1:], self.bus.tdi))

however this seems anomalous in TAP._elaborate_ios():

        with m.Elif(shift):
            m.d.posjtag += io_sr.eq(Cat(self.bus.tdi, io_sr[:-1]))

ah.  right.

http://openocd.org/doc/html/TAP-Declaration.html

-ircapture NUMBER

The bit pattern loaded by the TAP into the JTAG shift register on entry to the
IRCAPTURE state, such as 0x01. JTAG requires the two LSBs of this value to be
01. By default, -ircapture and -irmask are set up to verify that two-bit value.
You may provide additional bits if you know them, or indicate that a TAP
doesn’t conform to the JTAG specification.

so this, if i am reading it correctly, indicates that when you "set" the IDCODE
shift register, it must have been pre-loaded with a default value of 0b00001

the *old* (previous) shift-ir must have been set (at reset) to "0b000001".

where at present i am finding that it is *all* 1s.

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