[Libre-soc-bugs] [Bug 490] Complete peripheral set including litex for first functional POWER9 Core

[bugzilla-daemon at libre-soc.org]

https://bugs.libre-soc.org/show_bug.cgi?id=490

--- Comment #6 from Luke Kenneth Casson Leighton <lkcl at lkcl.net> ---
//--------------------------------------------------------------------------------
// Auto-generated by Migen (731c192) & LiteX (35929c0f) on 2020-09-18 23:11:06
//--------------------------------------------------------------------------------
module sim(
    output reg serial_tx,
    input wire serial_rx,
    input wire sys_clk,
    output reg [12:0] sdram_a,
    inout wire [15:0] sdram_dq,
    output reg sdram_we_n,
    output reg sdram_ras_n,
    output reg sdram_cas_n,
    output reg sdram_cs_n,
    output reg sdram_cke,
    output reg [1:0] sdram_ba,
    output reg [1:0] sdram_dm,
    input wire [7:0] gpio_in,
    input wire [7:0] gpio_out,
    output reg spi_master_clk,
    output reg spi_master_mosi,
    output reg spi_master_cs_n,
    input wire spi_master_miso,
    output reg sdcard_clk,
    inout wire sdcard_cmd,
    inout wire [3:0] sdcard_data,
    output reg spisdcard_clk,
    output reg spisdcard_mosi,
    output reg spisdcard_cs_n,
    input wire spisdcard_miso
);

ha!  this is progressing much faster than i expected.

Staf: for GPIO what is the definition of the IO pads?  should we do
very simple 8x GPIO-in and 8x GPIO-out, and not try to mix the two?
i am tempted to go this route because i means not having to write
any Litex code.

if we try a GPIO bi-directional IOpad it would mean having to write
some Litex code to add the CSRs for switching the direction, and
to output verilog code-fragments maybe actually adding that to
migen (!)

i really do not want to do that.

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