[Libre-soc-bugs] [Bug 495] New: Add API to PowerISA spec simulation to properly handle [partially] undefined results in tests

[bugzilla-daemon at libre-soc.org]

https://bugs.libre-soc.org/show_bug.cgi?id=495

            Bug ID: 495
           Summary: Add API to PowerISA spec simulation to properly handle
                    [partially] undefined results in tests
           Product: Libre-SOC's first SoC
           Version: unspecified
          Hardware: PC
                OS: Linux
            Status: CONFIRMED
          Severity: enhancement
          Priority: ---
         Component: Source Code
          Assignee: lkcl at lkcl.net
          Reporter: programmerjake at gmail.com
                CC: libre-soc-bugs at lists.libre-soc.org,
                    programmerjake at gmail.com
   NLnet milestone: ---

As mentioned in:
https://git.libre-soc.org/?p=soc.git;a=blob;f=src/soc/fu/div/test/test_pipe_caller.py;h=9c4ba3feeceb834cfb87869d0c7d764660e74b64;hb=fe09321a98f193a629d873a8ea055cc72ba949ff#l14

The python simulation of the PowerISA specification needs to grow new API
interfaces to allow tests to correctly ignore cases where the PowerISA spec
doesn't actually specify which output values are correct.

I think the API should track undefined values at the bit level, allowing tests
to match the parts of the output that are specified, while knowing to ignore
the bits that aren't specified. A relatively easy way to do that is adding a
validity mask to SelectableInt and setting `undefined` to have all bits
invalid. We can probably assume that all non-bitwise operations can just
generate completely undefined results (or just raise an exception) if they
encounter partially undefined inputs.

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