[Libre-soc-bugs] [Bug 490] Complete peripheral set including litex for first functional POWER9 Core

[bugzilla-daemon at libre-soc.org]

https://bugs.libre-soc.org/show_bug.cgi?id=490

Luke Kenneth Casson Leighton <lkcl at lkcl.net> changed:

           What    |Removed                     |Added
----------------------------------------------------------------------------
           Priority|Highest                     |High
           Severity|blocker                     |normal

--- Comment #1 from Luke Kenneth Casson Leighton <lkcl at lkcl.net> ---
ok i cranked the priority down just a leeetle bit :)

i also just committed some preliminary changes, cut out the pins not needed,
put in that verilog stuff we talked about 

commit 093ddebb6ba44f3edd291d699d775c6821b8d620 (HEAD -> master, origin/master)
Author: Luke Kenneth Casson Leighton <lkcl at lkcl.net>
Date:   Wed Sep 16 22:54:15 2020 +0100

    make a start on LS180 platform

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