[Libre-soc-bugs] [Bug 469] Create D-cache from microwatt dcache.vhdl

[bugzilla-daemon at libre-soc.org]

https://bugs.libre-soc.org/show_bug.cgi?id=469

--- Comment #36 from Luke Kenneth Casson Leighton <lkcl at lkcl.net> ---
(In reply to Cole Poirier from comment #0)

> ***Must follow up on nmigen SRAM attributes***

bit of research shows that "ram_style" is an attribute hint passed through to
synthesis.

further, that it is possible to pass a dictionary "attrs" to nmigen Signals.

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