[Libre-soc-bugs] [Bug 488] New: Build test serdes on 180nm test chip for oct2020

[bugzilla-daemon at libre-soc.org]

https://bugs.libre-soc.org/show_bug.cgi?id=488

            Bug ID: 488
           Summary: Build test serdes on 180nm test chip for oct2020
           Product: Libre-SOC's first SoC
           Version: unspecified
          Hardware: All
                OS: All
            Status: CONFIRMED
          Severity: enhancement
          Priority: ---
         Component: Hardware Layout
          Assignee: lkcl at lkcl.net
          Reporter: programmerjake at gmail.com
                CC: libre-soc-bugs at lists.libre-soc.org,
                    programmerjake at gmail.com
   NLnet milestone: ---

I found a paper describing a voltage-controlled delay element with differential
inputs and outputs that can operate at about 100ps delay at 350nm and about
10ps delay at 28nm, I was thinking that we might want to try building a PLL
where the VCO has 4 outputs all 90deg apart based on 4, 8, or 12 of those delay
elements connected in a ring oscillator where one of them is wired in an
inverting configuration by swapping output wires. We could then build a
high-speed serdes based on the VCO's 4 outputs triggering 4 D-FFs with the D
input wired to the high-speed input data for the deserializer and with a
similar set of 4 FFs with Q and not-Q wired up to a pile of and-or gates that
build a differential-signal-based (for equal propagation delay) 4-input xor
gate where the output is the serialized signal.

http://jultika.oulu.fi/files/nbnfi-fe2018121851276.pdf

If we have time, I think we should try to build those circuits on the 180nm
october tapeout and see how fast we can run it, how much power it takes, how
much area it takes, etc. I'd estimate the required area to be much less than
1/10 mm^2 and the required power when running to be in the range of 200mW. I'd
guess we can achieve somewhere around 5-20Gb/s over one wire in 180nm.

The frequency can be reduced to near zero by reducing the delay elements'
control voltage to near zero, so we won't need to add and gates in the delay
loop or something.

-- 
You are receiving this mail because:
You are on the CC list for the bug.