[Libre-soc-bugs] [Bug 416] dec and tb POWER9 SPRs needed

[bugzilla-daemon at libre-soc.org]

https://bugs.libre-soc.org/show_bug.cgi?id=416

--- Comment #2 from Luke Kenneth Casson Leighton <lkcl at lkcl.net> ---
commit a645950fa2d3c64b63b187485034dbafd115a16d (HEAD -> master)
Author: Luke Kenneth Casson Leighton <lkcl at lkcl.net>
Date:   Sun Sep 6 12:13:16 2020 +0100

    add DEC SPR to CoreState and PowerDecoder, activate 0x900 interrupt

commit ee491651861ed89c44ced180189656b8a80fbee0 (HEAD -> master)
Author: Luke Kenneth Casson Leighton <lkcl at lkcl.net>
Date:   Sun Sep 6 12:50:47 2020 +0100

    move DEC and TB from StateRegs to FastRegs for several reasons
    first: SPR pipeline already has fast1 read/write
    second: a new DecodeStateIn/Out object would be needed
            instead just add FastRegs.DEC/TB to DecodeA/Out
    third: there is probably a third somewhere

commit 0df522b99d98618d9ff5f95f622dbd79267ae728 (HEAD -> master)
Author: Luke Kenneth Casson Leighton <lkcl at lkcl.net>
Date:   Sun Sep 6 12:56:48 2020 +0100

    add a DEC/TB FSM to TestIssuer

    this operates on alternative cycles, because it reads/writes from the
    Fast Regfile directly

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