[Libre-soc-bugs] [Bug 238] POWER Compressed Formal Standard writeup

bugzilla-daemon at libre-soc.org bugzilla-daemon at libre-soc.org
Mon Nov 30 08:49:48 GMT 2020


--- Comment #115 from Jacob Lifshay <programmerjake at gmail.com> ---
(In reply to Alexandre Oliva from comment #113)
> whether such bits, when present in an insn, queue up after bits that are
> already there, or reset the queue and start affecting the next insn, would
> have to be worked out.  there are upsides and downsides both ways: one
> favors keeping a long queue so that alignments for more insns per cycle can
> be precomputed; the other favors locality.  The latter, combined with a rule
> that only the last insn in the queue may contain additional decoding bits. 
> If the queue runs out, we return to traditional mode; ditto when we take a
> branch.

If we do need a separate instruction for filling up the 16-bit queue, I'd argue
for it to have absolutely no other effect (no setting status flags, etc.), that
way we can completely delete it at the decode phase, allowing us to issue more
instructions per cycle. This doesn't mean we can't have all 16-bit instructions
have a bit reserved for adding an entry to the 16-bit queue, since those are
otherwise full instructions that aren't a waste of issue space.

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