[Libre-soc-bugs] [Bug 238] POWER Compressed Formal Standard writeup

[bugzilla-daemon at libre-soc.org]

https://bugs.libre-soc.org/show_bug.cgi?id=238

--- Comment #103 from Luke Kenneth Casson Leighton <lkcl at lkcl.net> ---
(In reply to Jacob Lifshay from comment #101)
> one other thing:
> some assembly-level instructions are really pseudo-ops for more general
> instructions (e.g. `not r3, r5` is really `nor r3, r5, r5`), those mappings
> can be different for 10-bit vs. 16-bit vs. 32-bit.

there are also several ways to encode 'mr' in v3.0B.   addi rt, ra, 0 is just
one.

space in 10/16 bit modes is so tight that we do not wish to waste it with two
ways to achieve the same result.

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