[Libre-soc-bugs] [Bug 238] POWER Compressed Formal Standard writeup

[bugzilla-daemon at libre-soc.org]

https://bugs.libre-soc.org/show_bug.cgi?id=238

--- Comment #102 from Luke Kenneth Casson Leighton <lkcl at lkcl.net> ---
(In reply to Alexandre Oliva from comment #96)
> I'm surprised/confused by some proposed encodings in
> https://libre-soc.org/openpower/sv/16_bit_compressed/ that affect my attempt
> at implementing an accurate compression estimator.
> 
> - is it really the case that an operation as common as 'mr' can only be
> encoded in compressed mode using an 16-bit + 16-bit immediate encoding? 

this sentence is ambiguous

it could be interpreted as "a 32 bit compressed instruction where the 1st 16
bits is opcodes and the 2nd 16 bits is an immediate".  [this type of encoding
does actually exist in VLE and i am dead set against us including it]

there is no 16bit + 16bit immediate encoding.  there is the 1st level
length+mode identifier FSM.

unlike VLE, no 16 bit instruction indicates that "actually its length is 32 bit
and that after the 16 bit instruction opcodes there is a further 16 bits of
immediate"

there is however only one way to get to "full" 16bit mode and that is to go
first via the 10bit mode.

do you mean, "is the only way to gain access to a 'mr' operation to make the
transition through 10bit compressed into 16bit compressed?"

if so the answer is yes, because the space is so tight in 10bit i couldn't
think how to do it at the time.

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