[Libre-soc-bugs] [Bug 238] POWER Compressed Formal Standard writeup

[bugzilla-daemon at libre-soc.org]

https://bugs.libre-soc.org/show_bug.cgi?id=238

--- Comment #97 from Alexandre Oliva <oliva at gnu.org> ---
> what you propose sounds perfectly reasonable for single-issue designs of
10-20 years ago.

Err, what you appear to be objecting now is to the 16-bit N=M=1 encoding for a
16-bit immediate, which is not something I propose.

Considering that the monster alignment muxer has to deal with it (if we adopt
that sort of encoding), but it's not responsible for the translation from
16-bit to 32-bit instructions, I don't see that the alignment muxer would care
at all about what's in the 16-bit extension.  Therefore, the remapper could
very well use those bits for purposes other than just an extension of the
varying-width immediates already present in several of the immediate opcodes.

So, are you saying we can't afford to have the 16+16-bit immediate encodings
with N=M=1, or that there's some other reason, unrelated to the alignment
muxer, to avoid altogether using compressed-mode 16+16-bit instructions that
use the extension for purposes other than just extension of immediate operands?

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