[Libre-soc-bugs] [Bug 238] POWER Compressed Formal Standard writeup

[bugzilla-daemon at libre-soc.org]

https://bugs.libre-soc.org/show_bug.cgi?id=238

--- Comment #96 from Alexandre Oliva <oliva at gnu.org> ---
I'm surprised/confused by some proposed encodings in
https://libre-soc.org/openpower/sv/16_bit_compressed/ that affect my attempt at
implementing an accurate compression estimator.

- is it really the case that an operation as common as 'mr' can only be encoded
in compressed mode using an 16-bit + 16-bit immediate encoding?  (I gather it
is, because all of the Immediate opcodes have the N and M bits set to 1)

- or are encodings that don't have N or M explicitly named as such ones that
use those bits for other purposes?  i.e., the immediate opcodes, despite having
those bits both set, are 16-bit insns without an extra 16-bit immediate, and
also without an opportunity to switch modes for the next insn?

The logic I built into the estimator went by the instruction formats in 2.1.1
and general directions in 2.1, but as I get to the proposed opcodes, things
don't quite seem to fit.  Help?

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