[Libre-soc-bugs] [Bug 526] create dry-run 180nm GDS-II files for IMEC

[bugzilla-daemon at libre-soc.org]

https://bugs.libre-soc.org/show_bug.cgi?id=526

--- Comment #54 from Jean-Paul.Chaput at lip6.fr ---
(In reply to Staf Verhaegen from comment #53)
> (In reply to Luke Kenneth Casson Leighton from comment #52)
> > (In reply to Jean-Paul.Chaput from comment #51)
> > 
> > ok - can you add that to alliance-check-toolkit, and set up an example?
> > (is there a Phantom version of FlexLib that's publicly available? i was
> > under the impression that there would be!)
> > 
> > i'd very much prefer that we're "tracking" what you're doing (right up
> > to the point where the "real" (NDA'd) version of FlexLib is used) and
> > have full public replicability.

  I completely understand that. I *may* be able to provide an obfuscated
  version of FlexLib which should not infringe the NDA. But, two problems:

  1. It would take a little time (to be 100% sure that nothing under NDA
     is still present). And I am critically low on that.

  2. Even if [1] is fullfilled, Staf is against it at the moment, because
     of potential FUD from the foundry. And he do not want to take any
     action that could jeopardize his relationship with IMEC/Foundry.


> The FlexLib is designed to make use of possibilities of each technology as
> much as possible. Result is that the P&R results will differ for each
> technology. In that respect I think it is very difficult to make a replica
> technology that does not violate the NDA. Therefor I targeted FlexLib P&R
> results to be only reproducible by people who are under NDA.

  I beg to differ, I am confident I could make it, but time is short
  right now.


> What is planned is to provide the netlist + placement of the cells of what
> is taped. This information together with an implementation of the cells in
> an open technology like freepdk45 or Sky130 should allow full verification
> of the design:
> 
> * first given the netlist one should be able to verify that the logic is
> fully equivalent with the RTL design.
> * second given the placement + layout of the cells in open PDK should allow
> to verify that actual produced chip is the one that is taped by delidding an
> decapsulating the chip.

  You mean to provide the placement done with *FlexLib+real foundry* ?
  Because otherwise, the placements are likely to differ. And without the
  wiring, how do you intend to check the layout correctness ?

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