[Libre-soc-bugs] [Bug 238] POWER Compressed Formal Standard writeup

[bugzilla-daemon at libre-soc.org]

https://bugs.libre-soc.org/show_bug.cgi?id=238

--- Comment #81 from Jacob Lifshay <programmerjake at gmail.com> ---
(In reply to Alexandre Oliva from comment #79)
> I've just completed my first skimming over the entire 3.0 ISA.
> 
> The major mistake that I realized I made, and that I'm about to correct, is
> that I wrote in comment 58, that Luke kindly moved here from bug 529, that
> the primary opcode was in the MS byte, but it's actually in the LS byte.

The Power ISA has the Primary Opcode field in bits 0 through 5 -- the MSB end.
The Power ISA confusingly labels bits starting from bit 0 at the MSB end
through to bit 63 at the LSB end (assuming 64 bits).

Most of Libre-SOC's Python/nmigen code instead uses the more usual bit
numbering of 0 at the LSB end up through 63 at the MSB end.

One other confusing difference is that the PowerISA spec uses inclusive ranges,
yet nmigen/Python/Rust/C++/... all use half-open ranges by default:
low <= element < high

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