[Libre-soc-bugs] [Bug 238] POWER Compressed Formal Standard writeup

[bugzilla-daemon at libre-soc.org]

https://bugs.libre-soc.org/show_bug.cgi?id=238

--- Comment #64 from Jacob Lifshay <programmerjake at gmail.com> ---
I quite like the idea for encoding compressed instructions by having their
address be odd, as long as we retain the ability to be completely
backward-compatible with Power ISA v3.1 (including their 64-bit instructions)
in both BE and LE modes.

IIRC the opcode byte is the third byte in LE mode, so, we'd need to
conceptually decode bytes from aligned 32-bit words in instruction memory in
this order:

...
word N: 3rd, 4th, 1st, 2nd
word N+1: 7th, 8th, 4th, 5th
word N+2: 11th, 12th, 9th, 10th
...

where all instructions are made from a sequence of 1 or more bytes

-- 
You are receiving this mail because:
You are on the CC list for the bug.