[Libre-soc-bugs] [Bug 238] POWER Compressed Formal Standard writeup

[bugzilla-daemon at libre-soc.org]

https://bugs.libre-soc.org/show_bug.cgi?id=238

--- Comment #63 from Alexandre Oliva <oliva at gnu.org> ---
Sorry about your headache, I hope you get better soon.

I sense miscommunication here.  Regarding the attempts to use the 2 bits of the
mode-switching byte, along with another byte to try to encode some useful
instruction, is what I consider unnecessary complexity.

It has absolutely ZERO to do with the concerns of separate state needed to
disassemble.  Indeed, the use of 8-bit switch-mode insns that I have proposed
does not affect in any way the difficulties a disassembler might face when
pointed at a word holding a single 32-bit insn, two halves of 32-bit insns, 2
16-bit insns, one 16-bit insn and two halves of other 16-bit insns, or any such
thing.

Please don't conflate unrelated issues and, especially, don't reject ideas
based on assumptions as to their motivations, especially if the assumptions are
unfounded and, as it turns out, incorrect.

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