[Libre-soc-bugs] [Bug 523] demo program needed showing register dependencies

[bugzilla-daemon at libre-soc.org]

https://bugs.libre-soc.org/show_bug.cgi?id=523

--- Comment #19 from Jacob Lifshay <programmerjake at gmail.com> ---
(In reply to Luke Kenneth Casson Leighton from comment #17)
> the purpose of this bugreport was to aid and assist in evaluating register
> allocation strategies, saving considerable time in the hand-writing (4+
> hours) of markdown tables through writing extremely rapid prototype and
> throw-away one-off python code.

Ok, I had missed that the whole point was to have throw-away code. I think you
are greatly underestimating the complexity of code required to generate those
markdown tables currently on the wiki, I'd estimate something around 2-5k lines
of python would have been required. It currently has 2.2k lines of C++
(counting files in c-src but not c-src/c++), and it implements the simulator,
fetch pipeline, register renamer (I started with that model since I understand
it better), and 5 instructions (addi, bdnz, ldu, mtctr, and std).

> the idea to develop near-gate-level simulations far beyond cycle-accurate
> simulations is a hundred to a thousand times longer development time than
> the expected scope of this bugreport, and cannot be considered
> "documentation"

I agree that a simulator would probably not be documentation, however, the
additional code required beyond the code needed to generate those markdown
tables is not very much, I'd estimate 1.5-2x as much code (if implementing just
the same instructions). Therefore, I decided to write the code in such a way
that it is feasible to extend later.

> consequently i am closing it and returning the budget back to the parent
> "Documentation" bugreport.

Fine by me, we can figure that out later, if we decide that the code is useful
for documentation, or other stuff.

Some demo output (cleaned up slightly):

|Cycle|0|1|2|3|4|5|6|7|8|
|-|-|-|-|-|-|-|-|-|-|
|0x100: mtctr r4||Fetch|Renamed: mtctr h2 \<- h1|||||||
|0x104: ldu r9, 8(r3)||Fetch|Renamed: ldu h3, 8(h0 -> h4)|||||||
|0x108: addi r9 \<- r9, 100||Fetch|Renamed: addi h5 \<- h3, 100|||||||
|0x10c: std r9, 0(r3)||Fetch|Renamed: std h5, 0(h4)|||||||
|0x110: bdnz .L2|||Fetch|Renamed: bdnz h6 \<- h2, .L2||||||
|0x104: ldu r9, 8(r3)||||Fetch|Renamed: ldu h7, 8(h4 -> h8)|||||
|0x108: addi r9 \<- r9, 100||||Fetch|Renamed: addi h9 \<- h7, 100|||||
|0x10c: std r9, 0(r3)||||Fetch|Renamed: std h9, 0(h8)|||||
|0x110: bdnz .L2||||Fetch|Renamed: bdnz h10 \<- h6, .L2|||||
|0x104: ldu r9, 8(r3)|||||Fetch|Renamed: ldu h11, 8(h8 -> h12)||||
|0x108: addi r9 \<- r9, 100|||||Fetch|Renamed: addi h13 \<- h11, 100||||
|0x10c: std r9, 0(r3)|||||Fetch|Renamed: std h13, 0(h12)||||
|0x110: bdnz .L2|||||Fetch|Renamed: bdnz h14 \<- h10, .L2||||
|0x104: ldu r9, 8(r3)||||||Fetch|Renamed: ldu h15, 8(h12 -> h0)|||
|0x108: addi r9 \<- r9, 100||||||Fetch|Renamed: addi h3 \<- h15, 100|||
|0x10c: std r9, 0(r3)||||||Fetch|Renamed: std h3, 0(h0)|||
|0x110: bdnz .L2||||||Fetch|Renamed: bdnz h5 \<- h14, .L2|||
|0x104: ldu r9, 8(r3)|||||||Fetch|Renamed: ldu h2, 8(h0 -> h4)||
|0x108: addi r9 \<- r9, 100|||||||Fetch|Renamed: addi h7 \<- h2, 100||
|0x10c: std r9, 0(r3)|||||||Fetch|Renamed: std h7, 0(h4)||
|0x110: bdnz .L2|||||||Fetch|Renamed: bdnz h9 \<- h5, .L2||
|0x104: ldu r9, 8(r3)||||||||Fetch|Renamed: ldu h6, 8(h4 -> h8)|
|0x108: addi r9 \<- r9, 100||||||||Fetch|Renamed: addi h11 \<- h6, 100|
|0x10c: std r9, 0(r3)||||||||Fetch|Renamed: std h11, 0(h8)|
|0x110: bdnz .L2||||||||Fetch|Renamed: bdnz h13 \<- h9, .L2|

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