[Libre-soc-bugs] [Bug 155] a PLL is needed for the SoC

[bugzilla-daemon at libre-soc.org]

https://bugs.libre-soc.org/show_bug.cgi?id=155

--- Comment #24 from Luke Kenneth Casson Leighton <lkcl at lkcl.net> ---
(In reply to Staf Verhaegen from comment #23)

> The bypass of the PLL will be done by only using the MUX and buffers of the
> standard cell library.

a single Mux is what i put into a module called ClockSelect, this morning.

> If that doesn't work, chances of anything else
> working on the chip are negligible.

good point.

> I agree with Jean-Paul and Dimitri having the final say on this subject.

the current niolib does this:

* clocks are declared as clocks in a configuration parameter (sys_clk,
jtag_tck)
* for each clock, a clock tree **MUST** be made, covering the **ENTIRE** chip
* each clock will have its own ring created, for connection to the IO pads

what we may really need is:

* the clocks that are to be specified for creating H-Clock Trees are
  specified by a **SEPARATE** configuration parameter.

i will raise a separate bugreport about this.

-- 
You are receiving this mail because:
You are on the CC list for the bug.