[Libre-soc-bugs] [Bug 155] a PLL is needed for the SoC

bugzilla-daemon at libre-soc.org bugzilla-daemon at libre-soc.org
Tue Nov 10 12:56:54 GMT 2020


--- Comment #23 from Staf Verhaegen <staf at fibraservi.eu> ---
(In reply to Luke Kenneth Casson Leighton from comment #22) 
> i'm therefore willing to take that risk if Jean-Paul is happy with the
> implications, which i assume would be as follows:
> * that the external clock would *ONLY* go to the PLL (not as a Clock Tree)
> * that the PLL *output* is done as a Clock (H) Tree.
> if this is correct then the PLL should be positioned right next to where the
> external clock comes in.

The bypass of the PLL will be done by only using the MUX and buffers of the
standard cell library. If that doesn't work, chances of anything else working
on the chip are negligible.
I agree with Jean-Paul and Dimitri having the final say on this subject.

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