[Libre-soc-bugs] [Bug 336] ALU CompUnit needs to recognise that RA (src1) can be zero

[bugzilla-daemon at libre-soc.org]

https://bugs.libre-soc.org/show_bug.cgi?id=336

--- Comment #64 from Cesar Strauss <cestrauss at gmail.com> ---
(In reply to Cesar Strauss from comment #49)
> The ALU input interface uses a valid/ready protocol.
> 
> 1) The port is idle when valid_o and ready_i are both zero.
> 2) If valid_o is high but ready_i is low, we have a wait state.
> 3) When both are high, we have a data transfer, and the transaction ends.
> 4) It is illegal to keep ready_i high when valid_o is low.

After going through the Pipeline API, I realized case 4 is not illegal at all.

It should read:

4) If ready_i is high but valid_o is low, we have a wait state, from the
sending side.

I changed the test ALU input port to reflect this, by not forcing p.ready_o low
when p.valid_i is low.

commit 2b4b3a653806c543a17b5f6e6db2c00d24996210
Author: Cesar Strauss <cestrauss at gmail.com>
Date:   Sun Jun 28 18:38:03 2020 -0300

    Let p.ready_o be active while the test ALU is idle

    The valid/ready protocol doesn't actually forbid p.ready_o
    being active while p.valid_i is inactive. It just mean that
    the ALU is idle, and is ready to accept new data.

    This should help avoiding potential combinatorial loops from
    p.ready_o to p.valid_i.

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