[Libre-soc-bugs] [Bug 393] Hook up augmented-Wishbone Memory Bus to LDSTCompUnit (via PortInterface)

[bugzilla-daemon at libre-soc.org]

https://bugs.libre-soc.org/show_bug.cgi?id=393

--- Comment #24 from Luke Kenneth Casson Leighton <lkcl at lkcl.net> ---
here's the test class that connects Minerva BareLoadStoreUnit to a
harry ho wishbone-based SRAM:

[master 638a80f] add a test SRAM that lives behind a minerva
LoadStoreUnitInterface

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