[Libre-soc-bugs] [Bug 393] Hook up augmented-Wishbone Memory Bus to LDSTCompUnit (via PortInterface)

[bugzilla-daemon at libre-soc.org]

https://bugs.libre-soc.org/show_bug.cgi?id=393

--- Comment #22 from Luke Kenneth Casson Leighton <lkcl at lkcl.net> ---
oh, also, as you can probably see, i got fed up with LoadStoreUnitInterface
names not being clear which were inputs and which were outputs :)

i went through minerva core.py and also loadstore.py and ended up independently
confirming what you had identified as input and output.

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