[Libre-soc-bugs] [Bug 199] Layout using coriolis2 main core, 180nm

[bugzilla-daemon at libre-soc.org]

https://bugs.libre-soc.org/show_bug.cgi?id=199

Luke Kenneth Casson Leighton <lkcl at lkcl.net> changed:

           What    |Removed                     |Added
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           Assignee|lkcl at lkcl.net               |Jean-Paul.Chaput at lip6.fr

--- Comment #2 from Luke Kenneth Casson Leighton <lkcl at lkcl.net> ---
here's the diagram and page containing notes:
https://libre-soc.org/3d_gpu/layouts/coriolis2_180nm/

the first thing to note: there are quite a lot of Register Files
and there are quite a lot of Function Units.  therefore, as
there are quite a lot of unique Register File Ports, there are
also quite a lot of PriorityPickers (exactly one PP for *each* port).

i would recommend that every Function Unit's inputs and outputs
be on the same "side", because those inputs and outputs ultimately
have to go to the Regfiles, which is a single location.

the only exception to this is the LDSTCompUnit, which has the
additional connectivity to L0CacheBuffer, through which access
to Memory is attained.

LDSTCompUnit can have the memory access on the opposite side of
the registers.

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