[Libre-soc-bugs] [Bug 397] design and discuss user-tag flags in wishbone to provide phase 1 / 2 "speculative" memory accesses

[bugzilla-daemon at libre-soc.org]

https://bugs.libre-soc.org/show_bug.cgi?id=397

--- Comment #2 from Jacob Lifshay <programmerjake at gmail.com> ---
(In reply to Luke Kenneth Casson Leighton from comment #0)
> the requirements are - and this is not optional - that memory requests be
> subdivided into two phases:
> 
> 1) checking whether the request *CAN* be completed - WITHOUT EXCEPTIONS - if
>    it were to be permitted to proceed
> 
> 2) allowing the memory request to proceed.

There are some peripherals where they only error after proceeding to the point
where it's impossible to cancel a request, so, our memory request state diagram
needs to properly handle that, without just hard-locking the CPU or creating an
inprecise interrupt.

This would involve waiting until non-speculative for non-cachable memory
addresses and potentially serializing operations. Cachable memory that is known
to be in the cache can be speculatively read and non-speculatively written in
parallel, no serialization required (unless using memory fences/atomic ops).
Cachable memory that is in the cache is also known to not cause memory
exceptions (assuming MMU translation and checking has already been done and
ignoring ECC cache memory failures).

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