[Libre-soc-bugs] [Bug 393] Hook up L2 Cache to Wishbone/LDST Wrappers

[bugzilla-daemon at libre-soc.org]

https://bugs.libre-soc.org/show_bug.cgi?id=393

--- Comment #18 from Luke Kenneth Casson Leighton <lkcl at lkcl.net> ---
(In reply to Yehowshua from comment #13)
> I won't be of much use on LDST until I've read through the link below...
> Unless - you have something wishbone that you want me to plug into.
> https://groups.google.com/forum/#!topic/comp.arch/cbGAlcCjiZE
> 
> Luke, I would suggest not going for full wishbone compliance.
> Just do something that **works with LiteX DRAM sitting below the LDST
> unit.

ok.  think it through.  what classes are needed?

> It can really be quite simple - even if the resulting FSM isn't fully
> functional.

indeed.  that is not the issue.

what components are needed?  describe the *full* chain.

think it through.

bear in mind that no matter what is created, they *have* to talk - interface to
-
PortInterface [the libre-soc equivalent of LoadStoreInterface].

forget *everything* in l0_cache.py

describe to me - in your own words - *every* component, every piece of code,
outlining the *full* connectivity between each and every component.... starting
at:

     PortInterface.

go from there.

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