[Libre-soc-bugs] [Bug 393] Hook up L2 Cache to Wishbone/LDST Wrappers

[bugzilla-daemon at libre-soc.org]

https://bugs.libre-soc.org/show_bug.cgi?id=393

--- Comment #12 from Yehowshua <yimmanuel3 at gatech.edu> ---
Well - we don't have to do full wishbone...

If we targeting Litex DRAM, sub, cycle, addr, re, and data
really suffice I think.


Basically, LiteX DRAM behaves kinda like Harry Ho's SRAM.

And now I'm confused.
L0 Cache **isnt** the even odd cache things?

At some point, we should have a call so I can better understand this.

For now, I can make a dead simple cache that looks like a memory.
I'm afraid I won't be much help on LDST as my conversation will generate
more questions.

I really wish thing were more simple.

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