[Libre-soc-bugs] [Bug 393] Hook up L2 Cache to Wishbone/LDST Wrappers

[bugzilla-daemon at libre-soc.org]

https://bugs.libre-soc.org/show_bug.cgi?id=393

--- Comment #6 from Luke Kenneth Casson Leighton <lkcl at lkcl.net> ---
ok so back on topic here: the two interfaces that are *nearly* the same
are:

* LoadStoreInterface from minerva
* PortInterface from libre-soc l0cache.py

these are what need "matching up".

these are the signals from LoadStoreInterface:

        self.x_addr = Signal(addr_wid)
        self.x_mask = Signal(mask_wid)
        self.x_load = Signal()
        self.x_store = Signal()
        self.x_store_data = Signal(data_wid)
        self.x_stall = Signal()
        self.x_valid = Signal()
        self.m_stall = Signal()
        self.m_valid = Signal()

        self.x_busy = Signal()
        self.m_busy = Signal()
        self.m_load_data = Signal(data_wid)
        self.m_load_error = Signal()
        self.m_store_error = Signal()
        self.m_badaddr = Signal(addr_wid-log2_int(mask_wid))

and these are the ones from PortInterface:

        # distinguish op type (ld/st)
        self.is_ld_i = Signal(reset_less=True)
        self.is_st_i = Signal(reset_less=True)
        self.op = CompLDSTOpSubset()  # hm insn_type ld/st duplicates here

        # common signals
        self.busy_o = Signal(reset_less=True)     # do not use if busy
        self.go_die_i = Signal(reset_less=True)   # back to reset
        self.addr = Data(addrwid, "addr_i")            # addr/addr-ok
        # addr is valid (TLB, L1 etc.)
        self.addr_ok_o = Signal(reset_less=True)
        self.addr_exc_o = Signal(reset_less=True)  # TODO, "type" of exception

        # LD/ST
        self.ld = Data(regwid, "ld_data_o")  # ok to be set by L0 Cache/Buf
        self.st = Data(regwid, "st_data_i")  # ok to be set by CompUnit

Data is a Record that contains a "data" and an "ok".

therefore:

* pi.is_ld_i == lsi.x_load
* pi.is_st_i == lsi.x_store
* pi.ld.data == lsi.m_load_data
* pi.ld.ok   == lsi.m_valid     (probably - just guessing here)
* pi.st.data == lsi.x_store_data
* pi.st.ok   == don't know
* pi.addr.data == lsi.x_addr
* pi.addr.ok   == lsi.x_valid   (probably)
* pi.go_die_i == {concept does not exist in LSI - *might* be lsi.rst}
* pi.busy_o  == lsi.x_busy      (probably - again, just guessing)
* pi.op.data_len == lsi.x_mask but **ONLY** after processing through LenExpand
* pi.addr_ok_o   == {concept does not exist in LSI, i don't think}
* pi.addr_exc_o  == lsi.m_load_error *and* lsi.m_store_error
* {nonexistent}  == lsi.m_badaddr

this leaves lsi.x_busy to identify - plus all of the other guess-work
signals.

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