[Libre-soc-bugs] [Bug 393] Hook up L2 Cache to Wishbone/LDST Wrappers

[bugzilla-daemon at libre-soc.org]

https://bugs.libre-soc.org/show_bug.cgi?id=393

--- Comment #3 from Luke Kenneth Casson Leighton <lkcl at lkcl.net> ---
(In reply to Yehowshua from comment #2)
> Some example memory connections.
> Will merge into SOC git repo later.
> 
> https://github.com/BracketMaster/nmigen-by-example

see bug #382, i have begun that process (and found a bug in the sram.py as
well).

the README btw is excellent.  it would be fantastic to have the same quality of
documentation in the documentation store known as the "wiki", for the project.

by being part of the project, this would help increase the readability of the
project and help us to gain more contributors, because people respect the
source of the information as a valuable resource.

although superb and exactly the kind of high quality readability that we need,
and i appreciate that there was a dependency (nmigen-soc) whch is now added to
git.libre-soc.org - unfortunately the high quality README has the unintended
side-effect of directing - diverting - attention *away* from our project.

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