[Libre-soc-bugs] [Bug 325] create POWER9 TRAP pipeline

[bugzilla-daemon at libre-soc.org]

https://bugs.libre-soc.org/show_bug.cgi?id=325

--- Comment #93 from Luke Kenneth Casson Leighton <lkcl at lkcl.net> ---
(In reply to Cole Poirier from comment #92)
> Hi Luke,
> 
> I added some code to TRAP in decoder.isa.caller but commented out because I
> didn't want to break test_caller.

given that absolutely nothing calls it, that is not possible.

therefore commenting it out is pointless and extra work.

only when a unit test is added will the cide actually be called.

when called, it will call uncommented code, which will fail, and you will have
achieved nothing of value.

if however you add the code, and the unit test in test_sim.py, you actually
have something to start comparing against.

that is progress.

adding commented out code is succumbing to lack of confidence :)


> I implemented most of the pseudo-code but
> felt like I was on very shaky ground as I didn't fully grok the way I should
> be implementing the pseudo-code for this function.

only by actually trying it, and getting the test_sim.py to check the PC, abd
SPRS SRR0 and SRR1 and the MSR against qemu will we find out.

until then it is guesswork.

> I think I need some
> guidance on how to set the 'TRAP exception type',

traptype? i did it already.  and added references to the 3.0B spec page.

> and review of my commented
> code to see if I'm on the write track.

yes looks perfectly reasonable to me.  may need to create a mirror msr_copy
function though.

will check tomorrow when it's not 3am

> Am I correct in my understanding that once this is done in
> decoder.isa.caller it should be added as two tests (twi, tw) in
> fu.trap.test_pipe_caller?

yyyep.  and also we need to add the sane to test_sim.py and check against qemu.

> After this all that remains for the TRAP pipeline is writing the formal
> proof?

yes.

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